Image-reject receiver architectures for radio frequency integrated circuits

The availability of high-speed CMOS processes allows increased system integration and low manufacturing costs. However high-speed CMOS processes degrade some circuit performance due to short channel effects and lower supply voltages. Therefore, circuit designers need to reconsider their architecture choices as well as new circuit design techniques with every new communication standard and integrated circuit manufacturing technology.; The thesis concentrates on image-rejection down-conversion architectures. Elimination of image-reject filters requires other means of suppression of the image band. A 90° phase shift is usually generated by means of quadrature mixing or on-chip polyphase filters. Quadrature mixing methods usually use digital and/or analog calibration for high image rejection performance. In general, RF phase splitters are either avoided in receiver design altogether or they are implemented in simple RC-CR form and as RC-based polyphase filters. RC-based structures are not very popular at radio frequencies due to their large loss. They also tend to use large chip area in an attempt to avoid mismatches in the circuit. A lumped element directional coupler can provide a 90° shift at RF, using less area with a smaller amount of loss. Using directional couplers at high frequencies also opens a door to new circuit possibilities. Designers can take advantage of on-chip hybrid couplers and combine RF front-end circuits in different ways that would improve the receiver performance as well as providing the phase shift required for image rejection. This study investigates techniques that allow designing image reject front-end down-conversion architectures using lumped element Lange couplers for the IEEE 802.11a frequency band.; The last part of the thesis explores an indirect approach to carrier generation: a VCO core operates at a fraction of f c where device gain is higher for a given power consumption, but the key technique is the use of a passive mixer as a frequency multiplier to generate a high frequency LO without increased DC dissipation. A 24GHz LO signal is generated from a 12GHz VCO cascaded with a 2X passive mixer, and a standalone 24GHz reference VCO is also implemented in 0.18 mum CMOS. The 24GHz designs exhibit equivalent phase noise, but use of the passive mixer enables a 4X reduction in power consumption and a 2X increase in tuning range.