The Research Of CMOS Current-Mode Radio Frequency Mixer

With the demand of the market for those wireless communications products ceaselessly growing, the requirements of the wireless mobile communications products are also higher and higher:lower voltage,lower power consumption, smaller size,higher performance,lower cost and so on.The RF front end, as a key block of the wireless communication, also requires more and more.Usually, the tradition RF front end is voltage-mode.With the development of modern integrated circuit technology, it was found that the bandwidth of current mode circuits is wild,and power consumption is low, and the performance of high frequency is so good.All these merits of current mode circuit are better able to meet the needs of the people for the circuit design. The design method of current mode RF front-end design has become one of the hot directions.Therefore,this paper mainly researches on the mixer, which is the key block of RF front-end receiver.A novel low-voltage high-linearity current-mode mixer is proposed.Such work as following has been done:Firstly,this dissertation makes an introduction on the working principle of the mixer, and a detailed description of the performance parameters of the mixer.And then two methods of designing mixer are proposed on the basis of the analysis of kinds of the typical mixer circuit.And then according to the former analysis,a novel 2.4GHz current-mode mixer circuit with low-voltage high-linearity is proposed.The features are shown as follows: (1)The mixer uses a parallel folded structure,of which the mixing core works in the sub-threshold region, and uses the LC resonant as an end.As a result, the circuit in the use of chartered 0.18μm CMOS process can work at 0.9V supply voltage;(2) Using the current mirror to amplify the input and output current signals,can not only reduce the V-I (voltage-current) and I-V (current-voltage) conversion,but also get an excellent linearity.When the supply voltage is 1 V,the IIP3 of the proposed circuit is 13.48dBm,and the conversion gain is-0.21dB,and the power dissipation of the entire chip is 5.3mW;(3)After improving the current mirror, when the whole circuit supply voltage also is 1 V,the other performances remain basically unchanged, but the conversion gain increases 0.23 dB,and the IIP3 is add up to 24.64 dBm. When the supply voltage has a±0.1 V fluctuation, the entire circuit performance basically has few changes.Finally, with the chartered 0.18μm CMOS RF process, the layout and back simulation have been done in the Candence layout design software.Compared with the front simulation results,the back simulation results is very good.