A fault-tolerant approach to test control utilizing dual redundant processors

A dual-redundant fault-tolerant test control system architecture has been designed, developed and demonstrated in a real time environment using low cost personal computers. A cost-benefit analysis has been performed comparing the relative benefit of this system to triplex and non-fault-tolerant systems for various applications. A survey of existing fault-tolerant control systems was performed to assess the relative cost and capabilities of currently available technology. Functionally identical implementations of a prototype proof-of-concept software design were constructed in two different languages and tested using a unit-under-test model. Bugs were injected into this model to verify the ability of the system to reliably detect anomalous test hardware operation. Simulated faults were introduced to verify smooth control transfer between primary and standby, both nominally and in the presence of hardware-under-test anomalies. Results indicate a significant improvement in system reliability, sufficient to justify the additional cost of the proposed duplex system for many potential users.