Research On Key Technology Of Fault-Tolerant Nanoscale Circuit Based On Statistical Model

For decades, the rapid pace of improvement in microelectronics has been based on the ability to exponentially decrease the minimum feature sizes used to fabricate integrated circuits(ICs). With the continuous miniaturization of electronic components, the CMOS process is now under development from deep sub-micrometer to nanometer. In nanoelectronics, the computational architectures will be suffered from a lot of structural faults and signal faults due to many reasons such as the physical limitations imposed by thermal fluctuations, power dissipations and quantum effects. Hence, the design of fault-tolerant circuit is concerned by researchers, and many different kinds of fault-tolerant structures have been proposed. The main focus of this dissertation is on the signal fault-tolerance circuit base on Markov Random Fields (MRFs) model, analysing for the fault-tolerant ability of combinational circuits and clock self-recovery technology in sequential logic.As the interference due to nosie can significantly affect the nano circuit performance, and the conventional CMOS design methodology cannot handle this noise problem appropriately. We apply MRF theory to cope with these signal errors and designgate-level circuits with significant noise immune improvment. The dissertation also extends the MRF model to the design of 8bits carry-lookahead adder(CLA), and analyzes the design complexity of the Sbits MRF_CLA. To demonstrate the proof-of-concept design, we have implemented the silicon-proven MRF chip, an 8bits MRF_CLA. The measurement results show that the noise-immunity value of the MRF design can be improved 24.5dB as compared to its conventional CMOS design. To analyse the behavior of the system level when some error occurs in the basic elements—gates, we combine the MRF theory with Probabilistic Transfer Matrices (PTM) efficiently to perfect the PTM theory for its application. The circuit designers can achieve the transformation relationship of signal clearly by the PTM, which can help them for circuits' analysis. Based on the PTM of the combinational circuits, we then propose various criteria to evaluate the circuits' error-tolerance capability. We also propose a new method to prove the validity of the PTM theory and criteria proposed by the dissertation, Simulation results show that the PTM and prosposed criteria can reflect the circuits' behavior and they are effective and suitable for computer-aidod design (CAD) tools development in nanoscale circuit and system design.To deal with the clock faults caused by noise, crosstalk and structure of the chip, the dissertation proposes a totally new architecture for clock recovery. Very simple circuit is designed for time-to-voltage converter with transforming the error of time to the error of voltage. The transformed voltage is very convenient for error detecting. The voltage is then processed by self-adaptive peak value capture circuit to realize the voltage comparison and clock self recovery. The simulation measurement shows that circuit is simple and power efficient, which is the key characteristic for IC design, so the proposed circuits is very suitable for integration to VLSI design to realize clock recovery.