A 24GHz fully differential transmit PLL in a 0.13mum process

In this thesis the design of a 24GHz fully differential transmit phase locked loop (PLL) is reported. The circuits are implemented in a 0.13mum process.; This transmit PLL consists of a voltage-controlled oscillator (VCO), a phase frequency detector (PFD), a charge pump (CP) and a down-conversion mixer, as well as an on-chip loop filter. All the blocks are fully differential.; The differentially tuned VCO is constructed using a complementary negative gm structure. The varactors in the VCO are implemented using accumulation MOS (AMOS) varactors to obtain higher Q and relatively large tuning range. The measured free running output frequency is 21.5GHz and the VCO gain is 588MHz/V.; The down-conversion mixer is implemented using a conventional Gilbert Cell topology. The most challenging part of this design was the high frequency single-ended to differential converter, which is utilized to convert the single-ended off chip LO signal into a balanced differential signal. After much research, a two stage differential pair used as a converter was found to be the best choice.; The PFD is constructed using current mode logic (CML) cells and the CP is driven by rail-to-rail signals. The frequency response was the major concern in the PFD and CP design. A CP with cascaded current sources is found to provide improved speed and current matching.; The measurement results showed the VCO and mixer work properly but the PFD and CP part fails due to a short circuit existing in the circuit which was caused by careless layout. This failure could be fixed by a laser cut.