VLSI architectures of LDPC based signal detection and coding system for magnetic recording channel

With the increase of areal density for magnetic recording, more advanced digital signal processing and error correcting codes are in demand for the next generation storage applications. Low-Density Parity-Check (LDPC) based signal detection and decoding have been attracting tremendous research interest because of their excellent error-correcting performance and highly parallel decoding scheme.; This thesis investigates the construction of LDPC codes which not only achieve very low sector error rate with a high code rate, but also facilitate for VLSI-implementation to meet the high throughput requirement of hard disk drives. A high speed FPGA simulator for the magnetic recording channel detection and decoding is developed to assist the analysis of the error floor issue. Based on extensive simulations, we postulate empirical guidelines for designing randomly constructed high-rate regular QC-LDPC codes with low error floor.; A low-complexity pipelined partially parallel encoder hardware architecture is developed. The encoding is performed based on the sparse parity check matrix and mainly involves a few sparse matrix-vector multiplications and a small dense matrix-vector multiplication.; Several VLSI architectures of LDPC decoder are proposed. The first proposed decoder architecture is based on standard sum product algorithm. This decoder architecture is enhanced to support more flexible trade-offs between decoding throughput and silicon area, especially allowing to implement high-rate QC-LDPC codes with low error floor for very high decoding throughput. To further reduce the memory requirement and complexity, a novel decoder architecture based on transformed Min-Sum algorithm is proposed. Comparing to the state-of-the-art of LDPC decoders, this design offers advantages in terms of silicon area, throughput and power consumption.