| The hardware/software co-design is a popular approach for accelerating various complex algorithms and similar software applications. The time critical portion of the data processing algorithms can be implemented using hardware accelerator to reduce the processing time. FPGAs provide ideal template for run-time reconfigurable designs. The powerful embedded system development platforms from Xilinx, loaded with integrated PowerPC processor core and high density Virtex-4 FPGAs, have made the hardware/software co-design very much practical. This research provides a comprehensive design process description of accelerating an algorithm for a package screening application. Several aspects of design process including implementation, simulation, debugging and hardware interfacing to reconfigurable computing platform are discussed. This research successfully attempts to exploit the intrinsic hardware speeds to improve the performance of an algorithm in terms of processing time. The results of the acceleration technique are presented, including speed of operation and resource consumption. |
