The work of this thesis was supported in part by National Defense Pre-research Foundation - "Digital Signal Processing Techniques in Real-time measurements", one of whose goals is to study the real-time performance of signal processing algorithms, especially of measurement algorithms.The thesis firstly addresses the real-time performance of spectral zoom analysis algorithms. Complex modulation based zoom algorithm is a classical one of such algorithms, in which samples are modulated, decimated, filtered, spectrally analyzed and re-sorted. In this thesis, complex analytical band-pass filtering based method is proposed to reduce the modulation complexity; Polyphase decomposition is used to reduce the filtering complexity; Uniform DFT filter banks based method exploits the center frequency distribution characteristic of filter banks to reduces the modulation and spectral resort processes. All algorithms are simulated in MATLAB to verify their function and realized with MS320C6711 DSK to measure their real-time performance. Simulation results are in accord with theoretical deduction.The algorithms proposed or improved can be used in high performance real-time spectral analysis instruments.Another focus of the thesis is to study the quantitative methodology for mapping signal processing algorithms on hardware architectures, concentrating on the algorithm-hardware mapping under the fixed resource constraint. Because of the NP complexity of mapping problem, the thesis studies two-step method: optimal scheduling of data flow graph and optimal processor mapping.The thesis uses 0-1 integer linear programming to construct algorithm-hardware mapping models. Based on bounds of data flow graph proposed by Barwell and Hodges, cost function combining iteration periodic bound with periodic delay bound and several constraints are proposed. The models successfully map 2-order IIR filtering algorithm on processor array with 4 processing elements. During the process, a linear and nonlinear programming software- LINGO is used to solve the model.The models are also modified to map algorithms on VLIW architecture signal processors. The thesis studies the data path structure of TMS320C6X and then constructs scheduling and mapping models for C6000 instructions. The models successfully map 2-order IIR filtering algorithm on TMS320C6X VLIW DSP.The proposed algorithm-hardware mapping models can be used in optimal design of real-time signal processing system. They can also be used in automatic optimized compiler of VLIW DSP. |