| Due to increasing operating frequencies and circuit densities, accurate and efficient signal integrity analysis has become a major limitation for high-speed VLSI design. Signal propagation effects such as delay, distortion, reflections, and crosstalk can seriously limit the overall performance of high-speed systems. Accounting for these effects in analytical device models is not always possible and subsequently, high-speed modules are characterized by tabulated parameters (Y, Z, S, or H), obtained either through measurements or rigorous full-wave electromagnetic simulations.;In this thesis, a novel algorithm is developed to produce a compact macromodel through delayed rational function approximations. The proposed macromodel provides a transient speedup of 10--50 times over conventional macromodels.;Prominent approaches for transient analysis of subnetworks characterized by tabulated data are based on approximating the data with rational functions and subsequently, synthesizing a SPICE compatible macromodel. However, for networks with long delays, these macromodels require high-order approximations. |
