An FPGA based digital radio for meteor radar applications

High speed analog to digital conversion and dedicated digital signal processors offer the potential to revolutionize the radio science community. The increase in sampling speed and computing performance has drastically improved the bandwidth of processing that can be accomplished digitally allowing a push of the analog-to-digital conversion process further up the RF/IF chain from baseband. As such, the advent of software radios and digital receivers has moved much of the RF/IF chain from analog processing to digital processing. Interest has been growing in the radio science community to develop new, more capable and flexible digital receivers, to replace aging analog technology and provide new instruments with capabilities never before considered. Evidence of this is the current receiver development work occurring in conjunction with the new AMISR (Advanced Modular Incoherent Scatter Radar) [33] system and other upper atmosphere facilities such as Arecibo [34] and Jicamarca [35].; The implementation goal of this thesis is to develop a simple, agile, and inexpensive multi-channel digital receiver for meteor radar applications that could also be extended to other applications suitable for deployment on unmanned aerial vehicles. This digital receiver design exploits the low complexity and power, small weight and size of analog receivers, and also offers simplicity and low cost over current commercially available digital receivers. It also exploits recent advances in analog-to-digital conversion to greatly reduce analog intermediate frequency processing.; This digital receiver uses a multichannel analog-to-digital converter from that encodes in the 20--50Msps range, a Field Programmable Gate Array (FPGA), and a High Speed USB Transceiver to digitize multiple analog signals. The FPGA is used to perform all conditioning and signal processing of the digital receiver, as well as to provide a memory interface to a USB Transceiver. The USB Transceiver allows a high-speed and low overhead data path to a host computer running the Linux operating system. Through the Linux operating system data can be saved to a mass storage device for post processing.; The reprogrammable nature of the FPGA provides tremendous flexibility for receiver configurations and requirements. The FPGA also provides a FIFO memory structure to ensure valid data, and glue logic for a USB interface to a host computer running a UNIX based operating system. Current USB specifications limit the combined output rate of all channels to 480Mbps and we have benchmarked the interface at 40MB/s using the Cypress FX2 USB interface and a host computer running the Linux operating system.