| This thesis will discuss the VLSI implementation of analog LDPC decoders. The good performance of LDPC codes and their intrinsic parallel decoding algorithm makes them suitable for high performance decoder design. Analog circuits are chosen due to their simpler circuits, smaller number of interconnections (less area and power consumption), the disappearance of iterations (faster convergence and higher throughput) and lower noise generation. However, in analog LDPC decoder design, an effective VLSI implementation method with good results remains a serious challenge for two reasons: (1) traditional analog design flow is not suitable for large-scale analog design, and (2) lack of universal optimization methods.; In this thesis, we propose an iterative optimization method that can be applied to an automatic analog design flow based on pre-built macro cells. This method simplifies the design process and optimizes the design result with the help of a placement and routing tool called First Encounter (FE). It is shown in this thesis total interconnection wire length can be used to evaluate the optimization result. In our case, with certain constrains (pre-built cells, parity-check matrix and preset layout configuration), the optimization aims to find an optimized position for each cell in order to reduce the total wire length. The final result shows that a 25% to 35% reduction in total interconnection wire length comparing to initial random placement can be achieved with this method. Unlike previous optimization methods, which are usually restricted to a certain type of code, this optimization method can accommodate different code types, and is more general. |
