| The rapid development of the modern electronic information technology makes the demand of high speed, low power consumption of data communication system more and more great.In the channel, with the improvement of rate, it certainly need to bring in more complex coding scheme and decoding algorithm, which can reduce the data error at the receiver caused by the high speed transmission.The performance of LDPC code is one of the most studied good channel coding scheme, but the iterative decoding of LDPC code has high computing complexity and computing power. In the case of a given power, it is difficult to use the traditional digital circuit to realize decoding. In recent years the researchers had found that decoding devices of LDPC codes based on the analog circuit have the characteristic of low power consumption, high efficiency and et al, it can greatly reduce the power consumption of the decoder of the LDPC code.In this paper,based on the extensive reading of a large number of papers involving factor graphs,the product algorithm and analog decoding technical data, we focus on the factor diagram and algorithm, and from the angle of the factor graph,the analog decoding problem of the LDPC codes is abstracted into a marginal function by sloving it through the global function, which gives a kind of brand-new explanation of the decoding of LDPC.This article also proved that we can use low degree of nodes to cascade the high degree of node so as to set up a modular structure of factor graph,which reduces the complexity of factor graph.According to the analog decoding algorithm, improve and optimize the structure of factor graph, which are reducing the consumption of resources.Finally, we build the simulation decoder through the analog circuit simulation model based on approximate Elmore delay method, the simulation results show that the performance of analog decoder of LDPC codes is very close to that of the decoder using BP algorithm. This also shows that the design of analog decoder is feasible. |
