Research On Optimization Method Of Analog Integrated Circuit

System-on-Chip (SoC) typically consists of both digital circuits and analog circuits. While the digital portion of SoC can be automatically designed with the help of well developed EDA tools, the analog part is still designed manually with only the help of SPICE-like simulators. As a result, the design of analog part has become the bottleneck of SoC design due to the lack of automation tools. All these clearly reveal a pressing need for analog EDA tools, especially for analog optimization tool. On the other hand, as semiconductor technologies scale to finer feature sizes, the increasing fluctuations in manufacturing process result in significant deviations of the actual performances of the circuit from the nominal one, and thus decreasing the yield of fabricated circuits. Therefore, uncertainty aware analog optimization has been becoming one of the most popular and difficult topics. Accordingly, this thesis is focused on the following two aspects:(1) In order to optimize the design parameters of analog integrated circuits not only efficiently but also accurately, this paper proposes a geometric programming method combined with model revision technique named MRGP. Applying this method, the design objective and constraints are formulated as posynomial model of the design parameters firstly. Then, geometric programming is iteratively utilized to optimize the device size, during which transistor-level SPICE simulations are employed to continually revise the posynomial model. An example of a widely used operational amplifier circuit is applied to demonstrate that the proposed method could achieve the SPICE-level accuracy without sacrificing too much efficiency when compared to the existing equation-based methods and simulation-based approaches.(2) Based on MRGP, this paper further proposes a model revised geometric prograrnming for analog circuit optimization considering process variations (MRGP-PV). MRGP-PV employs Response Surface Methodology to efficiently estimate the statistical distribution of circuit’s performances, and then utilizes the worst-case performances instead of the nominal ones to iteratively revise the posynomial model of geometric programming. By optimizing the worst-case performances of the circuit, MRGP-PV can finally achieve both optimal performances and high yield. Actual optimization example shows that the performances obtained by MRGP-PV satisfy the design specifications In the whole fluctuating intervals and also effectively avoid over design.