| The 6-4 GasP family of asynchronous circuits has been sought for its potential advantages of ultra-high performance and low power especially in the processor and the network on chip (NoC) domains. However, the use of these circuits is currently limited to custom design where extensive SPICE simulations are required to verify timing correctness and performance. In order to incorporate these circuits in the standard ASIC designs, it is essential to establish a more efficient CAD flow.;A fully automated characterization flow for developing timing libraries of single track circuits was shown in [13]. This thesis extends that flow to the GasP family of circuits and addresses the issue of validating the timing performance of these non-standard circuits using static timing analysis. We first discuss some of the relative timing constraints that were identified to ensure the desired working of the GasP control circuits. Then we discuss the characterization flow used for developing timing libraries for these circuits. Thereafter, we discuss how a static timing analysis tool, Synopsys PrimeTime, was used to verify these relative timing constraints as well as perform setup and hold checks on a substantial industry design. We conclude this thesis by identifying the worst cases of operation for the relative timing constraints which can be used for post analysis debugging. |
