Arps, The Motion Estimation Algorithm Implemented In Hardware,

With the development of multimedia , video compression technology has become a hot research field.MPEG-4 is the very fashion video compression standard. It achieves a significant improvement in bit-rate saving and rate-distortion performance compared with all existing compression standards.However,MPGE-4 complicated encoding process can not guarantee feasibility in real-time coding implementation, huge computation will cause huge power-consumption. The complexity of video coding system mainly lies on the motion estimation algorithm. So motion estimation algorithm which have high performance is hot research topic.The object of this thesis is to optimize the architectures of MPEG-4 motion estimation and to reduce its computational complexity. The architecture of MPEG-4 motion estimation is base on low-power algorithm. Flexible architecture is designed such that the use of MPEG-4 in different applications can be adjusted by easy-recombining.In this paper, we firstly discuss the principle and technical indexes of block matching motion estimation. Then we debate all kind of algorithms'performance. Finally we find is best motion estimation algorithm. This architecture is developed from a parallel VLSI architecture for FS. And they are designed, implemented and simulated with VHDL, ISE and Modelsim. According to the results we can conclusions: first, the motion estimation module designed in this thesis is correctly. Secondly, according to use of hardware recourses and clock frequency we prove the architecture designed for ARPS is advanced and real-time realizable.