An Improved Fast Motion Estimation Algorithm And Its FPGA Implementation

In the field of video compression, motion estimation is always an interestingresearch focus. Motion estimation utilizes the time-domain correlation of the movingimages to find the motion vector between two consecutive frames.In video codingalgorithms,the compression efficiency of interframe prediction that includes the motionestimation process is way higher than intraframe prediction,which rely on the spatialcorrelation of the image. However, motion estimation process brings a large number ofcalculations,make it restricted in the application level, fast motion estimation algorithmsappear to meet the growing need of real-time video transmission applications.The research in this paper is focused on how to reduce the large number ofoperations while maintain high search accuracy.The contents of this paper divide intotwo parts: how to achieve efficiency in motion estimation, and how to design andimplement the algorithm in FPGA.The work of this paper is as follows:1) Propose a fast motion estimation algorithm which based on a two-stagestructure proposed by W-H domain pattern matching algorithms,finding motionvectors between two frames by fast blocked projections and blocked fullsearch.Test the performance of the algorithm through a set of experiments,andcompare with the commonly used block matching algorithms.2) Use Verilog HDL language and QuartusII, Modelsim development tools onAltera Stratix EP1S25development board to finish the hardware structuredesign, implement and simulate every functional module, present functionaland timing simulation waveform. Every module turned out working properlythrough the waveform.Test the whole design,the waveform prove that thedesign implements the algorithm correctly,output give the right result ofmotion estimation.By setting the clock frequency and the hardware resourceconsumption.At last, discuss and analysis the shortcomings of the design.