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An analysis on the simulation of the leakage currents of independent double gate SOI MOSFET transistors

Posted on:2010-02-13Degree:M.SType:Thesis
University:Tennessee Technological UniversityCandidate:Moolamalla, Himaja ReddyFull Text:PDF
GTID:2448390002982260Subject:Engineering
Abstract/Summary:
The need for faster and more compact transistors is increasing each year. The design of transistors has been modified repeatedly by introducing new materials and new structures. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) technology has advanced from bulk Single-gate MOSFETs to Independent Double Gate (IDG) MOSFETs. The industry is moving from single gate transistors to multiple-gate transistors in order to retain control of ever shorter channels.;FinFET is a Double-Gated transistor, with two MOSFET gates tied together, that has been extensively developed and published worldwide. FlexFET is a newer Independently-Double-Gated (IDG) Silicon-On-Insulator (SOI) transistor with a JFET second gate that was first published in 2004. Research is still needed on this device in order to model the unique JFET bottom gate leakage in the FlexFET.;In this thesis, Silvaco's Atlas device simulation software is used to model the JFET bottom gate leakage currents in a FlexFET transistor. The parameters of the simulated device are: top gate work function= 4.5 eV, bottom gate work function= 4.9 eV, silicon thickness= 15 nm, top gate oxide thickness= 5 nm, channel length= 100 nm. This work determines that the bottom gate leakage currents in the FlexFET transistor are between 10-15-10 -16 A/mum. The operable bottom gate voltage range is found to be -1V to +0.7V in order to maintain bottom gate leakage current less than the sub-threshold leakage current of 10-7 A/mum. The channel doping and drain-gate spacing have little effect on reducing this leakage.
Keywords/Search Tags:Gate, Leakage, Transistor, MOSFET
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