| Delta-sigma analog-to-digital converters (ADCs) are suitable for many applications due to several advantages such as relaxed anti-aliasing filter, high signal-to-noise and distortion ratio (SNDR) and most important of all, reduced sensitivity to analog imperfections. This thesis introduces several structures to overcome loop imperfections and stability issues in delta-sigma modulators. First, a new multi-loop delta-sigma modulator is proposed to combine the relaxed circuit requirements of single-loop modulators with the stability of traditional multi-loop modulators. Measurement results of the prototype IC confirmed with opamps with loop gain of less than 30dB, SNDR of over 74dB can be achieved. Also proposed is a new single-loop modulator using a delay-free two-step quantizer enabling the input signals beyond the full-scale range to be processed by the loop. The fabricated prototype IC achieves over 75dB SNDR by allowing signals up to +5dBFS input signals. Third, is a modified dual-slope ADC which achieves first-order quantization noise-shaping. Combined as the quantizer of a second-order delta-sigma loop, the fabricated prototype IC achieves third-order noise shaping with 78dB peak SNDR. |
