| The thesis deals with the design of a digital predistortion system. This was implemented on a digital signal processor/field programmable gate array (DSP/FPGA) to provide an environment suitable for characterizing and linearizing power amplifiers to improve their operating efficiency. The characterization of the power amplifier is first outlined in simulation, and two behavioural models are used to characterize the power amplifier nonlinearity: the memoryless, and the memory polynomial models. To decrease the computational complexity of the memory polynomial algorithm in the DSP, two adaptive filter algorithms were introduced to solve for the polynomial coefficients. Both were shown to reduce the number of processing cycles while being able to achieve the same performance compared to the singular value decomposition algorithm. The DSP/FPGA solution was able to achieve the 3GPP linearity requirements for both a mildly nonlinear class AB power amplifier, and a highly nonlinear Doherty power amplifier. |
