Design Of Digital Predistorter For RF Power Amplifier Based On FPGA

Power amplifiers are essential components in communication systems and inherently nonlinear. The nonlinearity creates spectral growth beyond the signal bandwidth, which interferes with adjacent channels, causes the descend of communication system quality. Newer modulation methods, such as QAM or QPSK, are especially vulnerable to the nonlinear distortions due to their high peak-to-average power ratios. Therefore, how to reduce the nonlinear effect of power amplifiers is very important for the communication system. The traditional back-off method reduces the efficiency of power amplifiers dramatically. In order to achieve high linear and reasonably efficient power amplifier, linearization techniques are generally used. In different kinds of linearization technologies, the digital predistortion method is one of the most attractive ways due to its wide-use, stability, conveniences and flexibility. The main goal of our research is to analyze the nonlinearity characteristic of power amplifiers and design a kind of digital predistorter based on FPGA.The traditional DPD arithmetic based on look-up table is hard to implement for the complex synchronization operation. This thesis designs a kind of LUT-DPD arithmetic based on training signal, which does not need to do synchronization, therefore reduce the operation. And with this foundation designs a digital predistorter based on FPGA, optimize the arithmetic in order to reduce the cost.The nonlinear model of amplifier is extracted with the closed-loop method. The linearization algorithm is carried out based on the extracted power amplifier model. The whole system includes an RF part and a baseband part. This thesis focuses on the design of the baseband board. A training signal is generated in FPGA, subsequently is sent to DA and RF amplifier. The feed-back AD gets the distorted signal. Then the predistortion function in discrete form is generated by contract with the ideal amplifier gain, which can be stored in LUT. The LUT updated also follows such method. When the predistorter works, the input baseband signals multiply with the discrete predistortion function, accomplish the predistortion. The system simulation on ADS proves that such DPD arithmetic could improve the nonlinearity effect greatly.This thesis designs the pivotal modules based on FPGA, which include the address generate module, complex multiply module, training signal generate module and LUT generate/update module. After compiled by Quartus II 5.0, it uses 10% logic elements and 55% memory bits for Cyclone II EP2C20. Enough space is left to farther improve the DPD arithmetic.