FPGA Implementation Of Digital Predistortion Technology For Wideband Transmitter

Along with great-leap forward development of social information,people's needs for speed and efficiency of communication uninterrupted to increase.This has driven the uninterrupted progress of wireless communication technology.The new wireless communication systems ask greater rates of data and greater use of spectrum resources.In a wireless communication system,the use of spectrum resources is closely contact to the distortion of the radio frequency power amplifier.The lower the distortion,the greater the use of spectrum resources and the better the communication of information.Therefore,modern communication systems generally use linearization technology to reduce distortion of the output signal.Because baseband digital predistortion technology has low implementation price,easy implementation way,and excellent implementation effect,it is the most popular way of power amplifier linearization.However,the overall implementation cost is still relatively high,and there is still a large room for optimization.The main gist of this article is to reduce the resource consumption of the digital predistorter and realize the adaptive digital predistorter.First of all,the characteristics of various digital predistortion algorithms for RF power amplifiers are studied,and the function and resource overhead of various digital predistorters are dissected.On this basis,a plan to realize the adaptive digital predistorter is proposed.The proposed plan has the advantages of simplicity and nimble,low resource consumption and low cost.Finally,the proposed scheme is implemented and tested on FPGA.Specific work and improvement points in this article contains the following three points.(1)This article dissects the existing nonlinear models and algorithms.By comparing the complexity and modeling accuracy of the existing power amplifier models,it is found that these predistorters have large number of models,high complexity,long computational convergence time,and consume a lot of FPGA resources.(2)This article dissects the polynomial model in view of the coefficient sparse algorithm,and identifies the key points to reduce the FPGA resource consumption.A new adaptive digital predistorter based on the Fading Memory Polynomials(FMP)model is proposed,which is on account of the fading memory characteristics of power amplifier.FMP model and the MP model are simulated in the simulation software.The results make clear that the FMP model can significantly decrease the amount of coefficients of the predistorter under the case of ensuring the predistorter's degree of accuracy,so as to reduce the consumption of FPGA resources.(3)An adaptive digital predistorter based on FMP model is designed in FPGA.The experimental platform of digital predistorter based on FPGA+ARM structure is built.A digital predistorter is implemented on the Program Logic(PL)side of FPGA.The parameter calculation and transmission of digital predistorter are realized in the Program System(PS)end of FPGA.Experimental results state clearly that under the excitation of a QAM signal with a bandwidth of 20 MHz,relative to the traditional polynomial class,the proposed digital predistorter can reduce the consumption of FPGA logic resources by about 40% while the predistortion performance is degraded by only1.6%.