Asynchronous micropipeline synthesis system

Asynchronous (or clock-less) design has long been proposed as a solution to clock and timing convergence related problems. The biggest problem of asynchronous design acceptance has been identified in the absence of industrial quality Electronic Design Automation (EDA) support.;In this thesis we approach this problem with a framework for synthesizing asynchronous, pipelined circuits from conventional Register Transfer Level (RTL) specifications.;By modeling data propagation in synchronous RTL and in asynchronous pipeline with colored Petri nets, we show how the same data flow is controlled by fundamentally different mechanisms. We obtain the data flow model as a projection of synchronous RTL and asynchronous pipeline models and define a set of transformations to reconstruct either of the two models from the data flow. We prove that two live and safe models with the same data flow are flow equivalent regardless of the pipeline granularity. This transformation is the basis of re-implementing a synchronous RTL circuit into asynchronous pipeline. We extend the industry standard cell characterization format "Liberty" to support asynchronous cells implementing variety of existing handshaking protocols. Finally we develop re-implementation, analysis and optimization algorithms.;The proposed framework is implemented in Weaver---a proof of concept EDA flow using an industry standard RTL synthesis engine in synthesizing asynchronous pipeline from high-level hardware description language (HDL) specifications using an asynchronous cell library characterized using Liberty format with our extensions.;Distinct advantages of the approach presented in this thesis are related to the following contributions: (1) automated very fine grain pipelining capable of significant increase in computation performance (throughput); (2) support for standard HDL specification formats with no extensions and few limitations allow the reuse of existing designs; (3) support for a wide range of pipelining protocols, implementations and delay insensitive data encodings boosting the number of potential applications; (4) linear complexity of re-implementation allowing quick assessment of different design decisions; (5) systematic analysis providing comprehensive reports on the throughput bottlenecks of the asynchronous implementation and allowing goal based throughput optimization; (6) automatic test bench generation simplifying validation of the synthesized design; (7) target library extensibility, allowing incorporation of custom asynchronous IP.