Assembly process development for fine pitch (0.4 mm) package-on-package devices in a lead-free assembly environment

The ever increasing demand for miniaturization of electronic devices with high end functionality and larger memory capacities has driven the electronics industry to explore for novel and innovative technological solutions to satisfy the consumer needs. Increasing the circuit density on the printed circuit board (PCB) surface has reached a saturation point where circuit designers have no more real estate to accommodate devices in order to satisfy the growing consumer demands.;One of the emerging and most promising solutions is three dimensional (3D) packaging. Device manufacturers and circuit designers are now exploring innovative methods of using the space available in the 'Z' direction. The design conceptualization in 3D packaging is different from that of 2D packaging where incremental changes are made to increase the functionality and performance of the products. 3D packaging requires a new approach to logic design, package design and also considers the effect of these changes to the existing manufacturing, assembly, testing and inspection processes.;The package-on-package (PoP) technology is one of the 3D packaging techniques that is currently prevalent in the electronics industry. This technology is not new, however, most of the research work conducted in this field has been proprietary and so there are limited published resources, especially from a package assembly process perspective. This research endeavor focuses on the development of a robust and repeatable assembly process for fine pitch (0.4 mm) PoP devices in a lead free assembly environment.;This study includes validation of printing process parameters, development of placement process, identification of key equipment requirements, determination of reflow process window and assessment of the effect of reflow profile on the warpage characteristics of the PoP device. The design of experiments (DOE) approach was used in this study.;This study was able to provide a process window for the successful assembly of the PoP devices. A peak temperature range of 235°C to 250°C with a ramp rate range of 0.5°C/s to 1.25°C/s was able to form a good solder interconnection. The study also shows that a good solder joint was formed when the top package was dipped in either solder paste or flux.