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Design And Implementation Of Dedicated Neural Network Accelerators With Limited Performance And Power Consumption

Posted on:2021-02-27Degree:MasterType:Thesis
Country:ChinaCandidate:J W YuanFull Text:PDF
GTID:2518306494495334Subject:Computer technology
Abstract/Summary:PDF Full Text Request
With the continuous development of deep learning technology,deep learning has a wide range of applications in many fields.The current deep neural network model has become more complex,which means that the amount of parameters and calculations of the model are getting larger and larger,and the requirements for the hardware platform used to deploy the model are also getting higher and higher.However,tasks such as autonomous driving and remote sensing satellite target detection require detection and recognition of surrounding targets with extremely low latency.Data must complete the main calculations at the edge,but because the edge has very strict performance and power consumption restrictions on the hardware platform used.Therefore,in the case of limited power consumption and performance,building a dedicated FPGA neural network accelerator that can maintain higher accuracy and faster processing speed is the current research focus.Therefore,this paper designs and implements a dedicated FPGA neural network accelerator on the FPGA platform under the condition of limited power consumption and performance.The main work is as follows:Aiming at the target detection task as the starting point,this paper designs and trains a neural network model with less calculation and lower parameters.The neural network model obtained after training is perceptually quantify,and fixed-point parameters are used to replace single-precision floating-point parameters.After the optimization of the model,the amount of parameters and the amount of calculation can be greatly reduced at the cost of a slight decrease in accuracy.A set of configurable,portable,computationally intensive,and low-power neural network accelerators were built for the final model.In order to reduce the power consumption of the platform,the experimental development uses DSP multiplexing technology,and the accelerator architecture uses a hierarchical scalable design.In order to reduce resource usage,the accelerator uses streaming read and write technology for data and minimizes data reading.Writing technology,etc.The multi-module design of the accelerator can correspond to the calculation types in the neural network in the form of modules,which greatly increases the reusability of the neural network accelerator.The experiment results show that the accelerator has low power consumption,the standby power consumption is within 15 W,and the power consumption during normal operation is within 25 W.The accelerator has a relatively high computational load,and the number of operations per second is above 0.8T.In specific application experiments,it can efficiently identify ships on the sea surface.The recognition speed of ocean remote sensing images is more than 70 frames per second,and the accuracy rate can reach more than 90%.
Keywords/Search Tags:Marine Ship Identification, Neural Network Design, Low-Power Neural Network Accelerator, ZCU102
PDF Full Text Request
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