Research On NoC Test Planning Based On Hypercube Topology

Network on Chip,as a highly integrated multi-processor system on chip,breaks the performance bottleneck of traditional System on Chip(So C),but with the chip IP core(Intellectual Property)per unit area and the increase in the number of cores and the increase in the complexity of chip structures will bring a new round of tests to the test efficiency of chips.Therefore,in consideration of various constraints,with the goal of reducing test cost,how to implement efficient parallel transmission and test research has great research value,and has become an NP problem.In order to further optimize the test time and improve the test efficiency,this paper combines characteristics of the test structure and proposes a test planning method on the hypercube topology.This paper first improves the topology used in the test planning.Although the hypercube topology has the advantages of short network diameter,good symmetry and strong scalability,it has not been applied to NoC test research at present,so this paper proposes to apply it to NoC test planning research.Secondly,this paper designs an E-cube routing algorithm with partial adaptability according to the structural characteristics of the hypercube itself.The algorithm increases the utilization of routing nodes and communication links during the test.Different from the traditional deterministic routing algorithm,the algorithm proposed in this paper adopts the principle of low-dimensional priority,and uses the pre-judgment method to determine the state of the next routing node in advance,thus avoiding unnecessary routing waiting time.Finally,the improved hybrid algorithm is about to mix the improved particle swarm optimization(PSO)and the improved differential evolution algorithm(DE)to implement test planning research on NoC.In order to improve the characteristics of the algorithm,this paper introduces a reverse learning strategy to increase the diversity of the initial population,and adds a dynamic inertial weight w and a cross probability factor CR to improve the particle swarm optimization algorithm and the differential learning algorithm,respectively to increase the randomness and traversal of the population.The circuit on ITC'02 international benchmark circuit test set was used as the simulation experiment object,and the experiment compared the influence of the same IP core on the test time in different topology structure and test strategy,and a variety of circuits were combined for verification.The optimization efficiency between the proposed routing is analyzed and compared.The experimental results show that compared with othermethods,the test planning method proposed in this paper has a maximum test time optimization rate of 15.48%,which effectively shortens the test time.