Design And Implementation For The Hardware System Of High Performance Communication Main Control Board

The age of 5G has arrived.With the establishment of 5G trial networks,5G commercialization is being promoted.Wireless and mobile communications are entering the next generation.The main features of 5G of wireless communications networks are high data flow,massive terminals,low latency,low cost,and high efficiency.The above features are mapped to the hardware corresponding to advanced wireless transmission technology and high-performance and high-bandwidth baseband processing unit.So the baseband communication hardware needs to be updated urgently.This thesis develops the hardware of the main control board in the baseband processing unit under the 5G architecture.Based on the 5G protocol architecture,the complete development and design of the main control board has been describe from requirement introduction,system design to hardware board design and hardware testing.The main research contents of this thesis are as follows:This thesis is based on the definition of 5G baseband requirements,based on the main control board's 5G baseband business data processing requirements,selects MCU and Ethernet switching chips,and maintains clock synchronization,data storage,logic control and other functional modules of the main chip selection and architecture determination.Based on the 5G DU platform architecture,this thesis designs a high-performance and low-cost main control board that meets the needs of 5G.Draw the schematic and PCB layout.Test each function block to meet project requirements.This thesis developed the main control board for meets the 5G performance requirements.The design plans 24 10Gbps high-speed differential links and 102.5Gbps high-speed differential links.The design verification and optical serdes communication schemes such as SGMII,10GBASE-KR,SFI,XFI,etc.All the high-speed link has reached the theoretical communication rate and meets the design requirements of the project.Based on 5G requirements,this thesis designs a hot-switchable multi-clock source circuit on the board.And when all clock sources are out of lock,the constant temperature voltage-controlled crystal oscillator on the board can provide a stable clock of no less than 24 hours.This thesis developed a complete optimization and testing process for all high-speed interfaces on the high-performance main control board.By optimizing the signal integrity of the high-speed serdes and adjusting the electrical drive parameters of the physical layer,to reduce bit errors and packet loss.Perform external eye test and PRBS stress test with oscilloscope to ensure reliability.