Rf High Power Amplifier Based On Software Radio Baseband Signal Processing Platform Hardware Design And Implementation

Born in the middle1970s, the mobile communication system has moved towards tothe fourth generation after40years’development. By the end of2011, the global mobileterminal subscribers have broke through6billion. The mobile communication systemhas become an indispensable part of our life.However, non-constant envelope modulation and multi-carrier technology such asOFDM is widely used in new generation’s mobile communication system. Thesetechnologys will make signal’s Peak-to-Average Power Ratio much too high and theefficiency of the RF power amplifier low. More and more emphasis was put upon digitalalgorithms which are focus on improving the efficiency of the RF power amplifier, butfew articles is focus on signal processing hardware platform.Thus, this thesis proposes a high efficiency RF power amplifier signal processinghardware platform scheme, which is based on the software defined radio technology.First of all, this thesis reviews the history of two high efficiency RF power amplifierdigital assistive technologies, Crest Factor Reduction and Digital Pre-distortion. Then,analyse the current status of software radio signal processing platform product andbaseband hardware key technology. Combined with the above analysis and systemrequirement, we decided to use CPCI and FMC as the main technology of this signalprocessing platform.Secondly, the detailed design, which is including function, interface and powersystem realization, of signal processing module and data acquisition module was given.The signal processing module is composed of Xilinx Virtex-6FPGA, TMS320C6455DSP and P2020dual-core processor, while the data acquisition module is composed ofADS5400and DAC5682Z.Finally, the transfer speed of the interface between FPGA, DSP and GPP as well asthe noise characteristics of clock, ADC and DAC were measured. The result indicatesthat this platform has a bility to provide as much as480Mbyte/s data transmissioncapacity, the jitter of clock was optimized to844fs, the typical SNR of ADC is54.7dBFs, and the typical SFDR of DAC is63.2dBc.With characteristics of modularity and commonality, this signal processing platformnot only used as a high efficiency RF power amplifier digital algorithm platform, butalso used in some other projects such as a multi-airplanes communication system andone communication system protyping. It enrich the research of high efficiency RFpower amplifier and wireless communication signal processing platform, and has areferential value and commercial value.