H.264 Decoder And SOC Design For Real-time Video Transmission System

The 21 st century is the era of big data,and industries that revolve around big data have become the main growth points of emerging industries.Among them,the video business is a business type with a relatively large proportion of data.As people have more and more stringent requirements for the definition,fluency,and real-time of video images,real-time video processing and compression technologies have received more and more attention from the industry.At the same time,due to the rise of 5G,the demand for high bandwidth and low latency such as VR/AR is becoming more and more popular.This thesis aims at the SOC system design of the FPGA-based real-time video transmission system,and mainly carries out the following innovative design work: Based on the application requirements of the real-time transmission system,the SOC system platform is independently built,and some IP cores are independently designed.Based on the UVM general verification methodology framework,each IP core and SOC as a whole are verified.This paper first analyzes and implements the functions of the main components of the SOC,and designs and implements the SOC platform system including the on-chip interconnect AXI4 bus system,DMA,Gigabit Ethernet controller,DDR3 controller and interrupt controller.In the design of the H.264 codec IP core,this paper analyzes the video compression processing flow by studying the industry's mainstream video compression codec standards,and refers to the existing video codec hardware acceleration schemes for real-time video With the characteristics of high bandwidth and low latency of the transmission system,a video codec hardware accelerator based on the H.264 standard is designed.On the basis of design and implementation,this paper builds a verification platform based on UVM verification methodology,designs test cases for different IP cores.And using Xilinx's ISE development kit,the system-on-chip SOC was simulated and verified.