Research On Ultra Low Power Physically Unclonable Functions For IoT Security Application

Physical unclonable function(PUF)is an emerging hardware security technology that has flourished with the rise of the Internet of Things(IoT)in recent years.It has no storage,tamper resistance,randomness,low cost,low power consumption,small size and other advantages,which make it have broad application prospects in the field of hardware information security of the Internet of Things.However,IoT hardware devices often work in complex environments and have limited cost and power.These factors have imposed many restrictions on the application of PUF technology.Therefore,under the premise of ensuring that the PUF circuit can still have a high reliability,this work focuses on the ultra-low-power design for the application of PUF technology for IoT security.Firstly,this work proposes a solution with high energy efficiency and high temperature reliability based on the classic arbiter PUF(APUF).Current-starved(CS)inverters are inserted at the inputs of each multiplexer cell to reduce the skew and widen the distribution of the delay difference between two symmetric daisy-chained delay paths selectable by the input challenge.The CS-inverters are biased at the zero temperature coefficient(ZTC)point,making the accumulated delays of the two identical paths insensitive to temperature variations.A symmetric two RS latches based arbiter is proposed to overcome the asymmetric input and clock to output propagation delay of D flip-flop and the metastability problem of RS latch arbiter.By limiting the drain currents of CS-inverters to achieve ZTC,the power consumption of the proposed PUF is also reduced substantially.The performance of the proposed PUF design has been successfully validated by the responses measured from prototype chips fabricated in standard 65 nm CMOS process.The fabricated chips feature a compact silicon area of 3838 um~2 and low energy consumption of 2.74 pJ per bit at 25 Mbps,with measured uniqueness of 46.8%and native bit error rate(BER)of 0.8%.These physically measured figures of merit have outperformed previously reported measurements of PUFs.Secondly,this paper proposes a new energy-efficiency digitalization method for current-based PUF.This method uses a winner-take-all(WTA)scheme to simplify the analog-to-digital conversion process,which can overcome two disadvantages of power consumption and complexity of digitalization circuits.And because of two opposite outputs of WTA,as long as simple logic operations can eliminate the effects of systematic bias in real time by applying the unstable bits detection(UBD)method which can reduce the test cost of chips.This work validates effectiveness of the method by applying the design to a weak PUF based on a current array using a 65nm process.The measurement results show that static power consumption of the WTA circuit used to digitize mismatch currents is 0.902?w.When the throughput is 13.3Mbps,the all power is 5.42?W and the energy efficiency of this PUF is 0.41pJ per bit.Moreover,using UBD together with TMV5,both the unstable bit and the bit error rate(BER)at nominal conditions are reduced to 0%.At the temperature range of-40? to 120? and power supply range of 1.72V to 1.88V,BER is,respectively,0.31% per 10? and 0.14%per 0.1V which is decrease by 84.88%and 73.58%compared to the raw BER of both.The uniqueness of PUFs after stabilization is 50.1%.The response streams pass the NIST test and the autocorrection function with 95% confidence are-0.0324 and 0.0324.The above two types of PUF have high stability and passed the NIST randomness test.At the same time,the ultra-low power characteristics have reached the research purpose and met the design requirements.