Research On Model Attack Resistant Physically Uncloneable Functions

With the rapid development of the Internet of Things,a large number of embedded devices are widely used,and the information security of devices is more important than ever.Due to the characteristics of light weight and limited resources of embedded devices,the application of traditional cryptographic algorithms is limited.Physical Unclonable Functions(PUFs)have been extensively studied because they can resist physical attacks and are lightweight.PUFs can be used for key extraction,identification,and security authentication to ensure hardware security.However,PUFs,especially strong PUFs,are under the threat of modeling attack of machine learning.Machine learning can use a subset of challenge-response pairs to train a model with high prediction accuracy to overcome the security of strong PUFs.It has been discovered that although some existing modeling attack resistant structure of Arbiter Physical Unclonable Functions(APUF)lose reliability while improve the modeling attack resistance.Based on the research of existing schemes,a new improved structure of APUF,Racing APUF,is proposed in this thesis.This structure is based on multi-channel max(min)delay sub-chain multi-level cascaded,and has a variety of extended structures.The maximum and minimum delay operations based on AND or OR gates,enhances the resistance to modeling attacks by leading in nonlinearity and more model parameters.Racing APUF not only improves APUF’s resistance to modeling attacks,but also has reliability close to that of traditional APUF.The performance of Racing APUF is evaluated with two methods of software simulation and FPGA implementation in this thesis.The statistical analysis based on the probability distribution of the delay difference verifies that Racing APUF has the same reliability as traditional APUF when the number of max delay sub-chains and min delay sub-chains on each path are equal.Software simulation verifies that Racing APUF can improve the resistance to modeling attacks.Five kinds of expansion structures of Racing APUF is implemented on FPGA in this thesis.The experimental results show that the best performance structure is4-channel 2-level Racing APUF with 49.37% randomness,94.737% reliability,50.31% uniqueness,and75.6% prediction accuracy under evolutionary strategy modeling attacks.Racing APUF improves the antiattack ability with reasonable reliability,and can be applied to the authentication system of strong PUFs...