Design Of High Linearity Power Amplifier

In the contemporary wireless communication system,in order to improve the data transmission rate and spectrum utilization,more complex modulation schemes such as orthogonal frequency division multiplexing and quadrature amplitude modulation are adopted,generating signal with a higher peak-to-average power ratio(PAPR),which puts a higher requirement on the linearity of the power amplifier.At present,Long-term evolution(LTE)communication standard using orthogonal frequency division multiplexing modulation has been widely used in handheld devices.Therefore,it has an important research value to design a high linear power amplifier for LTE applications.The main objective of this thesis is to design a high linearity envelope tracking power amplifier for LTE handheld devices applications.The entire power amplifier consists of two cascaded main power stage,hybrid envelope modulator and adaptive gate bias circuit.Among them,the proposed hybrid envelope modulator includes linear amplifier stage,current sensing unit,hysteresis comparator,anti-shoot through buffer level and switch amplifier.A low-power and high-precision current sensing circuit structure is proposed by connecting one end of the sense resistor to the drain of the class-AB output buffer.According to the amplitude of the input signal,the high-performance supply modulator for providing a modulated supply voltage as a dynamic supply to the power amplifier to improve the efficiency of the back-off power region.At the same time,all the gate bias voltages of the two cascaded main power stages are changed with the amplitude of the input signal by using an adaptive gate bias circuit to reduce some of the amplitude-amplitude distortion of the envelope tracking power amplifier,which improve the linearity of the entire power amplifier.Therefore,through the use of envelope tracking and adaptive gate bias to improve the power amplifier linearity and efficiency simultaneously,which achieve a high linearity under the premise of considerable efficiency.The schematic design and layout design of the high linearity power amplifier and the verification of the pre-simulation and post-simulation are completed based on TSMC 0.13m CMOS process.For a LTE signal at 1.85GHz with a 10MHz bandwidth and a 16QAM 9.23dB PAPR,the post-simulation results show that the high linearity power amplifier achieves an average output power of 23.76dBm,an average power-added efficiency of 25.8%,a power gain of 22.36dB and an adjacent channel leakage ratio of-32.3dBc.The performance indicators are to meet LTE handheld device application,but also to meet the design targets.