The Study Of Radiation Hardened CMOS Image Sensor Readout Circuits

The CMOS image sensor is widely used in the application of various fields,with the advantages of low cost,low power and nice anti-jamming performance.It has extremely important research value in the application of spatial environment,especially in the fields of space exploration,remote sensing image and star sensor.As a key part of image sensor,readout circuit is very sensitive to radiation effect in space environment.As one kind of radiation effect,single event effect(SEE)has impact on both the digital part and the analog part.The main behavior form of SEE on digital circuit is single event upset,in analog circuit,a particle not only introduces imbalanced charge on the floating nodes,but also makes the analog signal perturbation,thus impacting the readout result.Therefore,this thesis mainly studies single event effects(SEE)on the readout circuit of the CMOS image sensors.This thesis researches the SEE effects on the CMOS image sensor firstly,and calibrating the parameter of double exponential pulse current source model according to TCAD-SPICE mixed simulation result.Then on the base of double exponential pulse current source model,this thesis studies sensitive nodes of the DPGA and ADC in detail.For DPGA,adopting Double-Path Radiation hardened design can mitigate effectively the influence of SEE on the floating node of operational amplifier.Meanwhile,for SAR ADC,an upset-tolerant D flip-flop with reset function and set function is designed,which can tolerant single event transients(SETs)at all input port.In addition,a new strategy to mitigate the effects of SETs on SAR ADC based on bulk built-in current sensors(BBICS)is presented.According to the mechanism of error occurrence,a series of BBICS and D Flip-Flops constitute a feedback control circuit,which is used to judge whether the SETs have a negative effect on SAR ADC and change the relevant timing sequence to correct the system state.The SAR logic wouldn't read the erroneous comparison result by shielding the edge of clock signal attached to the SAR logic.Under this method,the fault would be avoided to propagate to remaining conversions.This thesis designed the readout circuit of CMOS image sensors in 0.13?m process.The sampling rate of SAR ADC is 1Msps.Simulation result shows the effective number of bits(ENOB)is 9.89 bit and SAR ADC with BBICS can reduce the conversion error from 74 LSB to 2LSB.