Low Power Hybrid Logic Design Based On FinFET Device

Since the invention of semiconductor integrated circuits last century,under the influence of progress and updates of the integrated circuit technology and process,IC industry has been the rapid development in exponential growth rate followed by Moore's Law.The replacement of integrated circuits is characterized by the reduction of feature size?the increased chip integration and increased the frequency.However,as the process continues to shrink the size which inevitably lead to an increase in leakage current,resulting in an increase in the total power compution of the leakage power.The increase in chip size is beneficial to achieve more complex functions,but it will put forward to higher requirements in package and heat dissipation.Circuit frequency increases the chip faster and faster,but need to sacrifice power consumption in exchange for chip speed.Moreover,with the increasing application requirements,digital electronic systems for speed and power consumption requirements continue to increase,so it is significant to reduce circuit power consumption and to improve circuit speed as various research institutions of popular research topic.Full adder as a core componment of a high performance digital signal processor.it can not only complete the addition,but also involved in subtraction,multiplication and division operations which are widely used in large-scale integrated circuit designs.Full adder is an important unit who has a high performance requirements of digital signal processors,microprocessors and microcontroller systems,the good or bad performance of full adder is particularly important in the whole system performance.One-bit adder is widely used in the carry key path of the multi-bit adder,which is one of the important factors that affect the performance of the multi-bit adder.Therefore,it is very important to increase the speed of the adder and reduce the power consumption of the adder.This dissertation concentrates on studying the structure and operating characteristics of the TG-FinFET device and IG—FinFET device,on the basis of which to evaluat the advantages and disadvantages the full adder based on TG-FinFET device such as complementary symmetric logic one-bit full adder,differential logic one-bit full adder,CPL one-bit full-adder,TG logic one-bit full-adder,DVL one-bit full adder,M4 tructure hybrid logic one-bit full-adder,then we analyze the performance of the circuit,including the circuit area,the circuit power source and composition,circuit delay,power delay product.Then,in order to optimize the delay and power consumption of the circuit,this paper uses the M3 structure to study the full adder,the design of the three modules is implemented in different logic style,including TG-FinFETs and IG-FinFETs and analyzes its advantages and disadvantages.Under the condition of BSIM-IMG102.6,the HSPICE simulation tool is used to simulate and analyze the three modules at the input frequency of 1GHz,and the optimal design of each module is selected,A full-adder with the best performance based on hybrid logic of based IG-FinFET device M3 structure is built.Finally,the best performance based on the IG-FinFET device M3 architecture hybrid logic one-bit full-adder with the previous evaluation of the six traditional based on TG-FinFET device including complementary symmetric logic one-bit full adder,differential logic one-bit full adder,CPL one-bit full-adder,TG logic one-bit full-adder,DVL one-bit full adder,M4 tructure hybrid logic one-bit full-adder with area,power consumption,delay time,Power Delay Product to compare,but also highlights the new M3 structure hybrid logic one-bit full adder its small size,low power consumption,PDP small features for the integrated circuit designers to provide a reliable choice.