Design Of Array Readout Circuit Based On PLL-TDC

As one of the core technologies for laser ranging and 3D imaging applications,the infrared single-photon timing readout integrated circuit(ROIC)and the integrated GM-APD array can realize high-precision measurement of time-of-flight(TOF),thereby obtaining distance information of the measured target object.As laser ranging imaging applications continue to increase,ROIC systems should be designed with lower power consumption,higher detection accuracy,wider dynamics,and better linearity.However,as the scale of the array expands,the power consumption of the system increases sharply,and the performance improvement of the circuit is greatly limited.It is more and more difficult to expand the scale of the array while ensuring the performance of system.Aiming at the requirements of laser ranging and 3D imaging application,a type of PLL-TDC-based array ROIC is designed to realize three-dimensional imaging function by active ranging of target objects in this paper.Firstly,in order to meet the design requirements of high precision and low power consumption,a pseudo-three-stage local shared time-to-digital converter(TDC)is designed.The high segment and the middle segment are exclusive to the pixel,and the low segment TDC is shared by pixels.The high-segment is 7Bit periodic counting TDC,and the middle-segment is designed as a 2Bit asynchronous counter,whose output frequency-reduced clock is used as the counting clock of high-segment TDC.This way can not only maintain the range,but also can greatly reduce the counting power consumption of the high-segment TDC.The low-segment is a pixel shared 4Bit phase-resolved TDC,the split-phase signals is derived from the four phase-separated clocks of the PLL's output,to achieve high-precision requirement.Secondly,by improving the circuit of sampling structure in TDC,compressing its setup and hold time,simplifying circuit strucyure,making it more suitable for array TDC application,and low power optimization for TSPC architecture to reduce the power consumption of the pixel TDC.Finally,when designing the layout,selecting a suitable multi-supply comb-type double-ended power supply strucyure,utilizing delay matching design for important signals and suppressing crosstalk between high-frequency signals to improve the robustness of PLL-ROIC chip.This thesis is based on TSMC 0.35?m standard CMOS process and Cadence EDA to complete PLL and 16×16 ROIC system design,pre-simulation verification,layout design,post-simulation verification and tape verification.The test results show that under the condition of 3.3V power supply voltage,10 MHz reference clock,15.625 MHz low frequency transmission clock,20 kHz frame rate and normal temperature 27°C,the system is able to achieve a time resolution of 0.575 ns and a testing range of 2?s,and has-0.56LSB~0.57 LSB differential nonlinearity(DNL),-0.9LSB~0.57 LSB integral nonlinearity(INL).The chip's power consumption is about 151.7mW.The testing value of resolution is slightly increased compared to the simulation result,and other testing result basically meet the requirement of design index.