Design And Optimization Of Large-scale Vector Compilation Module In IC Test System

The test method widely used in the era of integrated circuit test systems is: the integrated circuit test system reads the test vector,applies input excitation to the pin of the chip under test,tests the output response of the pin of the chip under test,and compares the output response with the expected response to judge the test Whether the chip meets the standard.The number of test vector lines is in the hundreds of megabytes,and the content of the test is very complicated.Therefore,it is a widely used test vector input method to use a pattern file that supports storage and transfer of test vectors as input.The design and optimization of the large-scale vector compilation module in the integrated circuit test system in this paper aims to convert the pattern files storing the massive test vectors into executable binary files of the tester.In the design process,according to the design principles of software design with high cohesion and low coupling,this paper adopts the idea of sub-module design and control inversion interface design to ensure the readability and scalability of the program.The main research contents of this article are as follows:1.Aiming at the problem of slow access to massive test vectors,the test vector storage format is designed;according to the characteristics of the design format,the advantages and disadvantages of storing test vectors in binary format and HDF5 format files are compared;HDF5 format is selected as the target format of the test vector file in this paper.2.Aiming at the problems of slow speed and large memory consumption during the compilation of massive test vectors,this paper compares the two schemes of syntax analysis tree and unbuffered embedding action.Through performance analysis and experimental comparison,a hybrid implementation scheme is proposed.The vector declaration area that occupies a large amount of calculation in the pattern file adopts an unbuffered embedded action method with a small memory footprint and calculation amount;Adopt a clearer and simpler syntax analysis tree to achieve.3.In response to the problem of G4 grammar rule file design,design Teradyne T language format test language rules;according to the characteristics of test language rules,teradradar T language format pattern files are divided into functional areas;design scan pin declaration area and scan Syntax and lexical expressions in the vector declaration area.Aiming at the problem of diversified scan vector formats,by analyzing the scan vector format(character format,hexadecimal format),and mode(1-bit,2-bit),a method of uniform format is proposed.4.To deal with the complex problems of scan vector logic processing,analyze the scan vector format(character format,hexadecimal format),pin type(si,so),pin mode(1-bit,2-bit),and propose a scan vector format Unified method;analyze the scan vector attribute(serial vector)and ordinary row vector attribute(parallel vector),and propose a serial-parallel vector conversion method.5.Test and verify the vector compilation software to ensure the correctness and performance of the vector compilation software to meet the technical specifications of the project.After testing,the vector compilation software designed in this paper implements the addition of scan chain functions and the compilation of massive test vectors,and realizes the analysis of 128 M row vector depth and 1024 column vector breadth.