The Design And Study Of Memory Test Algorithm

With the development of deep sub-micron and other high-tech technology, storagein the SoC and the status of all integrated circuit products accounted for more andmore important. Memory chip capacity is more and more big, the integration isbecoming higher and higher, making internal memory transistor is more and moreintensive. It is due to the high density of wiring, storage element such as highcomplexity and high working frequency. Storage structure determines some kinds ofchip can’t use direct physical to test. Is the only way for the state of the storage unit toread and write, and then with the correct state of storage unit, and the contrast andcomparison, this leads to failure of physical forms into a logical form. In the face ofmore and more testing requirements, develop and efficient testing algorithms becomethe focus in the present.March SS algorithm, this paper obtained can cover all static and dynamic failuresof March SD algorithm. The algorithm with high fault coverage, the test complexity islow, to further improve the yield of chips, chip testing time and cost has the very vitalsignificance.In order to validate the March test performance and efficiency of the SDalgorithm, this paper also gives a memory tester, the design and implementation of thetester can be applied to all March test of the algorithm. Overall architecture USES thecurrent relatively popular design of virtual instrument technology, the underlying theFPGA logic circuit is used to realize the vector applied for memory chips and resultsreturned, PC interface using LabVIEW graphical programming language, algorithmanalysis and test vector generation, and intuitive to show the whole test process.Through this test system, can compare various algorithms of test performance andefficiency.