Research On Dynamic Fault Test For SRAM

With the widespread and ever increasing use of embedded memories in System-on-Chip (SoC),embedded memory has always been concerned in both industry and academia. With the decrease ofthe size of memory, these devices are prone to new defects due to get the highest storage density andaccess speed. However, the complexity of the memory makes fault modeling and testing not a trivialtask. Classical memory test solutions cover the so-called static faults, but are not sufficient to coverdynamic faults that have emerged in the latest VDSM (Very Deep Sub-Micron) technologies. So theresearches on the dynamic faults have significance and practical value.The main content of this paper is research on the dynamic fault test technology, the paperpresents as follows:(1) The simplified SRAM is built and the selection of parameters. In order to reduce thesimulation time, the considered memories are simplified version that include a reduced set ofcore-cells and the peripheral circuits as pre-charge devices and write drivers. Through this simplifiedcircuit testified by the simulation that the circuit has the correct read, write and maintaining datafunction. Due to the simulation carried out in TSMC180nm process and the core-cells with W/L ratiolimit, the size of the transistors are choosed.(2) The research on the faults caused by the resistive-open defects in the core-cell. Firstly, thecore-cell is introduced, and then the faults in the core-cell are analyzed, then mainly research on thedynamic Read Destructive Fault(dRDF), obtained by simulation found the relevent among the numberof read operations, defect size and the cycle time. Finally, the static fault simulation is also carried outand compared the difference between static and dynamic fault.(3) The research on the faults caused by the resistive-open defects in the pre-charge circuit.Firstly the pre-charge circuit is introduced, and then the faults in the pre-charge are analyzed. Wemainly research on the Un-Restored Write Fault (URWF) and Un-Restored Read Fault (URRF),through the simulation confirmed that test sequence can effectively test the fault and URWF is moreeffectively.The whole proposed simulations were used TSMC180nm process. Furthermore, the180nmprocess was used for the first time. Finally, the simulations and verification are through the Hspice.