Research And Implementation Of Multi-channel Synchronization Technology For PXIe Integrated Circuit Test System

The integrated circuit industry is the core of the information technology industry.As the operating frequency and scale of integrated circuits continue to increase,integrated circuit testing has become increasingly difficult.Automatic Test Equipment(ATE)based on automatic test technology has become the main method of integrated circuit testing due to its advantages of fast test speed,flexible test methods,and significant economic benefits.As one of the key indicators of ATE,synchronization accuracy is especially important as the test rate of ATE continues to increase.The PXIe integrated circuit test system digital test module developed in this project has a maximum test rate higher than 200 MHz,64 channels,and a single chassis synchronization accuracy of less than 1ns.It also has the advantages of multi-chassis cascading,small size,light weight,and low cost.This article combined with many related research tasks undertaken during the study of the master's degree,in the process of developing the digital test module of the PXIe integrated circuit test system,launched high-speed test vector synchronization output technology,single chassis module synchronization technology and multi-chassis cascade synchronization technology.Deep research:1.High-speed test pattern synchronization output technology.When testing the pattern output,it is necessary to determine the effective time interval of the vector and the return test result collection interval according to the six edge timing information,so the high-speed test pattern synchronization output is affected by the access speed of largecapacity timing information on the one hand,and on the other hand The processing speed of test vector waveform synthesis is affected.This paper analyzes the different implementation schemes and principles of these two aspects.On this basis,the actual output of different methods are compared,and the impact of different implementation schemes on the synchronization effect is discussed.2.Single chassis timing positioning and synchronization technology.In the testing process of integrated circuits,multi-channel joint testing is often required,and timing positioning and signal synchronization between channels are crucial.This project proposes two solutions for timing positioning,one is to use Serdes to achieve highprecision edge positioning through high-speed digital stepping,and the other is to use an external delay chip to achieve digital delay.This article discusses the advantages and disadvantages of different implementation solutions.For the single chassis synchronization problem,this subject is mainly achieved by synchronous calibration of the reference clock and synchronous calibration of the trigger signal.3.Multi-chassis cascade synchronization technology.Involving the problem of multi-chassis synchronization,this topic designs a synchronous trigger module to provide synchronized clocks and trigger signals for different chassis modules to make up for the problem of the clock and trigger signals of different chassis backplanes not being synchronized.This paper presents the test verification results of the relevant synchronization indicators of the digital test module of the PXIe integrated circuit test system,indicating that the system meets the test requirements of high-speed digital integrated circuits and implements digital integrated circuit testing in a low-cost manner based on the PXIe bus.