Research On Optimization And Design Space Exploration Of TAGE Branch Predictor

Branch predictor has long been a cornerstone of modern deeply pipelined,wide-issue microprocessors.Improving branch prediction accuracy not only increases throughput of the pipeline by reducing the misprediction penalty,but also reduces the instructions execution on the wrong path to save energy.For the tremendous number of instructions in modern programs,even modest improvements in branch prediction accuracy can bring great performance improvement.For the realization of state-of-the-art TAGE branch predictor in the microprocessor,this paper do design space exploration and optimization.The author's major contributions are outlined as follows:1.The performance of complex TAGE implemented in various RAM size processor is explored.This paper first defines design space exploration problem of the TAGE under the constraints of given RAM size and maximum global history register length.Then,based on the trace-driven simulation,the improved Particle Swarm Optimization algorithm is used to efficiently explore the specific parameters,rewarding design parameters with high prediction accuracy under RAM ranging from 0.125 KB to 4KB.For the traces of this paper,the parameters under the 1.5KB RAM explored by our algorithm can achieve adequate accuracy.The performance loss is considerably small if we reduce the RAM resources from 8KB to 1.5KB.In addition,the misprediction rate of 1.5KB TAGE are reduced by 63.41% compared to 1.5KB Bi-mode.And,0.25 KB TAGE has almost the same accuracy with 4KB GShare.2.Based on simulation environment in Championship Branch Prediction,this paper presents BPSim,a fast simulation environment for branch predictor based on trace driven,combining accuracy,area,and power consumption.Within this environment,the design parameters of the TAGE branch predictor with superior performance are automatically explored by the given RAM size and GHR length as input.3.SimpleBP,a lightweight prediction simulator based on trace driven is designed.It leverages the SystemC language to simulate branch predictor at clock cycle granularity.The CACTI tools is introduced to evaluate area and power consumption.Using SimpleBP,this paper first make some hardware design analysis in a 64 Kbits storage budget with new added features(feedback delay,fetch width and RAM port number).The experimental results show that the prediction accuracy loss is less than 2% when the feedback delay increased.Under the same RAM area,when fetch width modified,various traces show different accuracy changes.When the area used for dual-port is saved to construct more entries of the subpredictors,the accuracy improvement is 2.4498%.Then,considering these new features,this paper do example optimization exploration of RAM size and subpredictors number through SimpleBP,and the results show many meaningful differences with the results simulated through other simulation platforms.