The Research Of Strategy To SOC Design Space Exploration Based On Multiobjective Evolutionary Algorithm

The availability of large numbers of transistors on a chip has lead to the growth of IP (Intellectual Property) based design SOC (System-on-a-Chip) architectures. Many IP based SOC design approaches focus on mapping an application onto a previously designed complex SOC architecture built from an existing IP by configuring and extending the architecture, representing a configure and execute methodology. Such a parameterized SOC architecture is supported by a programming simulation and emulation environment, and may be provided as HDL source code, as an actual chip, or both. Due to the varieties of IP and the conflict of IP parameter, the SOC design space is very complex. An important SOC design work is the configuring of all cores' parameters, such that the architecture is tuned for the application, i.e., the software running on the SOC architecture, and for the power, size and performance constraints of SOC. One main task of the SOC system-level synthesis is design space exploration. The essential of the task is finding the optimal set of solutions to a multiobjective optimization problem.The classic solution to multiobjective optimization problem is using objective function linearity aggregation or Pareto based approach. These kinds of methods usually aggregate some subobjective function into vector function so as to convert multiobjective problem into single objective. The most defect of these approaches is that the optimized result is a single solution, not Pareto-optimal set of solutions. The advantage of the Evolutionary Algorithm is that it explores parallel numerous Pareto-optimal solutions corresponding to the objective space node by regarding solution set as population.Based on the analysis of SOC system-level synthesis and multiobjective evolutionary algorithm theory, we proposed a new design space exploration strategy to find a tradeoff of power and execute time for an application running onthe parameterized SOC architecture. The strategy uses IP parameter interdependency to reduce the design space and chooses exploration algorithm to explore design space according to the threshold of space size. The strategy is proved to be able to find better Pareto-optimal configuration effectively, and at the same time accelerate the speed of the design space exploration compared with sensitivity analysis strategy and exhaustive search algorithm.