Study Of Novel Gate-All-Around RFET And Its Application In Integrated Circuit

With the rapid development of ultra-large-scale integrated circuit technology,GateAll-Around transistors are expected to replace Fin FET and become mainstream devices at 5nm nodes and below.The development of Moore's Law is accompanied by huge economic investment,technological barriers and economic constraints,which will cause Moore's Law to reach its physical limit in the next ten years.Novel devices are coming out in the post-Moore era.Reconfigurable field effect transistors(RFETs)rely on their structural advantages to control the carrier polarity in the channel,and different voltage configurations to achieve the rotation of the device's N-type and P-type states.On the basis of traditional electronic information processing methods,circuits with fewer devices and more complex functions can be realized by using RFETs.However,RFET,as bipolar devices,face problems such as large off-state currents,degraded onstate current,and large subthreshold swings.This paper presents a novel asymmetric drain underlap-channel extension at drain end(UCED-RFET).This device can greatly increase the on-state current and suppress the off-state leakage current by virtue of its structural advantages.In addition,based on UCED-RFET,this paper studies its performance in logic gate circuit,and designs a novel of SRAM cell,which can effectively solve the contradiction between reading and writing.The main research work and results of this paper are as follows:Based on the existing RFET structure and the optimization ideas of traditional Schottky-Barrier field effect transistors(SB-FET),this dissertation designs a novel asymmetric reconfigurable transistor.With the help of TCAD numerical simulation tool,the device fabrication process is designed.The characteristics of electrical doping make the realization of UCED-RFET in industrial manufacturing possible.Compared with symmetrical underlap-channel extension at source and drain end RFET(UCESD-RFET)device,the on-state current of UCED-RFET is improved by nearly two orders of magnitude,and the ION/IOFF of the UCED-RFET device can reach more than 109.In this dissertation,the DC and AC characteristics of the UCED-RFET are simulated.The results show that,compared with TFET devices,UCED-RFETs exhibit better thermal stability under variable temperature conditions.In addition,the effects of Spacer materials and gate dielectric materials on the performance of UCED-RFET are also studied in this paper,and the results correlated with the scaling properties are also reported.Based on the UCED-RFETs,this article explores its performance on basic logic circuits such as inverters and ring oscillators.Studies have found that UCED-RFET devices can effectively reduce the polarity gate input capacitance by approximately 50%,and significantly reduce the logic effort in the delay evaluation of logic circuits.Utilizing the unequal bidirectional saturation current of UCED-RFET,the designed SRAM cell based on UCED-RFET can improve the read static noise margin by about 37.3%.The work of this paper has published in IEEE Transactions on Electron Devices,which has important reference significance for optimizing the design and application of RFET devices.