Research On Hardware Implementation Method Of High-rate Polar Codes

Polar code is an error correcting code that can be strictly mathematically proven to reach the Shannon channel capacity when the code length approaches infinity.Because of the excellent performance of the polar code,after a fierce competition in 2016,it was selected by the standards organization as the control channel coding scheme for 5G-eMBB scenarios.Polar code is an important research direction for future mobile communication systems,and it is also a current research hotspot for 5G.Turbo codes and LDPC have undergone sufficient development in error correcting codes,and these two are currently widely used.The development of new things requires a process,as does the polar code.Since being proposed by Arikan in 2008,the polar code has experienced rapid development in just over ten years.However,the SC decoding algorithm performs poorly when the code length is short,and the decoding delay and resource occupation remain high when the code length is large.Designing high-rate polar code encoder and decoder is a inherent challenge of diversified 5G application scenarios,a sharp increase in data volume,and low latency.This paper first analyses the concept of channel polarization and the basic principle of polarization code encoding and decoding,then compares several methods of constructing polarization codes.In the aspect of encoder,the performance of system encoder is compared with that of non-system encoder,and then a high-rate system encoder based on two-level non-system encoder is designed.In terms of encoders,this paper first analyzes the hardware structure of several SC decoders.Then,this article analyses the popular fast SC decoding algorithms and compares them with standard SC decoding.Next,based on the fast SC decoding algorithm,this paper designs nine kinds of fast decoder hardware structures,optimizes the hardware resource allocation,and analyzes key hardware indicators such as decoding delay,throughput rate,and hardware resources in detail.Finally,the Xilinx-VC709 development kit was used to establish the communication hardware link,and the hardware simulation and the actual FPGA board were used to complete the test.Research shows that,compared with standard SC decoders,under the premise of consistent decoding performance,the decoder designed in this paper based on fast SC decoding algorithm can significantly increase the throughput and reduce the decoding delay.Finally,this article uses hardware to implement the system encoder and fast SC decoder,and gives the actual hardware decoding delay and resource occupation report,and completes RTL-level simulation and actual board testing.