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Design And Implementation Of Adaptive Verification Platform Based On UVM

Posted on:2021-01-16Degree:MasterType:Thesis
Country:ChinaCandidate:X Y WangFull Text:PDF
GTID:2428330620464149Subject:Engineering
Abstract/Summary:PDF Full Text Request
Along with the rapid development of science and technology,the integrated circuit's process size has been down to 5 nm,the integration degree of the chip has been continuously improved,the scale is increasing,and the function is very rich.However,it is precisely because of its complex functions that there may be understanding deviations in hardware design,and it is these deviations that may lead to the failure of the flow sheet and cause huge economic losses,so the importance of verification is obvious.The traditional verification method will not only consume a lot of manpower and material resources,but also consume a lot of time,and when similar verification is needed,the platform is often not reusable and needs a lot of changes.UVM verification methodology is one of the most important methods to solve this problem.The advantages of high efficiency,sufficient verification.This paper presents the design procedure and method of setting verification points and DDR4 parameters in each functional scenario of chip running.It also provides a UVM verification platform to verify the original data storage controller and intermediate data storage controller,including the programming,communication mode,data transmission path of each component in the platform,and designs the excitation generator to make the generation of excitation easier.Only through txt file input data,can automatically generate each level of verification header files,reduce the workload of verification,improve the efficiency of verification,and then collect coverage results,analysis of design defects and problems,and then regression testing,continuous iteration to gradually improve the completeness of verification.Finally,every function point in each function scene is verified,the typical simulation waveform is selected to display,and the code and test vector are designed iteratively according to the waveform,and the code coverage rate is 100%,and all the function points are realized,and the design function of the two storage controller modules is ensured correctly.On the basis of ensuring the completeness and correctness of verification,the construction time of verification platform is shortened,and the efficiency of verification is improved.
Keywords/Search Tags:UVM, validation platform, DDR4, data storage controller
PDF Full Text Request
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