Design Of RF Power Amplifier Based On GaAs Process

The development of communication technology provides people with great convenience.The rapid increase of data traffic also requires faster communication rate,lower delay and more reliable communication quality.To achieve these requirements,high PAR OFDM multi-carrier modulation technology has been adopted from 4G LTE to the upcoming 5GNR.This requires the power amplifier(PA)of the RF front end to maintain low nonlinear distortion and high efficiency within a large power back-off range.Therefore,multi-mode,multi-band,low-distortion,high-efficiency RF power amplifier chips used in mobile communication equipment have a broad application market,and related research has important significance.Based on the analysis of the basic impedance matching theory,a variety of broadband impedance circuits are further studied with the help of Smith chart,and the implementation and impedance transformation of these circuits are discussed.These impedance matching circuits can achieve the expansion from narrowband to broadband matching while maintaining low insertion loss.The matching method is used in the broadband power amplifier chip circuit proposed in this thesis and achieves the expected results.In addition,a common harmonic suppression path in the inverse class F power amplifier is designed in the output matching circuit to filter out the second harmonic and improve the linearity.In this thesis,a highly linearized and fully integrated broadband power amplifier based on Ga As HBT process is presented.The chip is assembled using a flip method.The PA,consisting of a driver stage and a power stage,operates from 1.71 GHz to 2.05 GHz.To coverage of multiple uplink bands,multi-stage matching networks have been employed.The measurement results show that the power amplifier exhibits a linear power gain of 30 d B.Besides,when the operating voltage is 3.5 V,the output power is 28 d Bm,and a 10 MHz 50 RB QPSK LTE signal is chosen as the input signal,the power added efficiency(PAE)and the adjacent channel leakage(ACLR)of this PA is about 37% and-38 d Bc,respectively.The PA chip size with on chip bias circuit is only 0.755mm×0.8mm.