Research On On-chip Tracing Debug Technology Based On System Bus For Multi-core SoC

DFD(Design-for-Debug)is an important part of SoC design.In recent years,with the continuous improvement of performance requirements for embedded system,the integration and complexity of SoC is increasing.At the same time,it also brings many challenges for embedded debug design,mainly reflected in the contradiction between the large number of signal observation requirements and limited hardware resources,the debug requirements for parallel operations in multi-core system,and the controllable design of debug components.Since the system bus is an important component in multi-core SoC to realize the communication function of each module,and its internal transmission information can reflect the interaction and concurrent behavior of each module in the system.So in view of the above problems,we study the on-chip tracing debug technology based on the system bus to meet the system analysis and debug requirements of complex multi-core SoC.After analyzing the embedded debug requirements of multi-core SoC in detail,we first research and design the data path of bus tracing debug for non-invasive and observability requirements.Its overall structure includes the bus information acquisition module,the tracing data compression module,the data storage module and the export port.For the acquisition of tracing information,we research two common on-chip bus interconnection architectures,and research and design the bus information collection scheme of the most widely used AHB and AXI as a research case.In order to alleviate the pressure of on-chip storage,we compress the bus information,and propose a reverse-encoding algorithm for the circular storage mechanism of the circular buffer to achieve reverse encoding compression of tracing data,and the simulation case verifies that the data compression module we designed can achieve a compression ratio of 43% for AHB tracing data and 36% for AXI tracing data.In order to realize the visual function of tracing debug,we display the bus transmission behavior and system interaction behavior in the form of lists and graphics through software design.Secondly,we research and design the control path of bus tracing debug for controllability requirements,and its overall structure includes JTAG debug interface module,tracing control module and APB.We design the JTAG debug access interface by adding tracing debug commands and related data registers on the basis of reusing the JTAG port pins.As the master of APB,the tracing control module could access and configure the relevant control registers of each debug component through APB,so as to realize the control of bus tracing debug function.In addition,we also design two trace trigger modes to control the start and termination of the tracing debug function,and design the trace source configuration registers for the crossbar interconnect bus to control the amount of tracing information from the data source dimension.Finally,we conduct function evaluation and example analysis on the bus tracing debug design.We build an eight-core SoC system based on RISC-V processor,and integrate the bus tracing debug design into the multi-core system to evaluate the data-level,transaction-level and behavioral-level tracing functions.In addition,we used these three tracing functions to conduct performance analysis and case study on the interaction behavior and concurrent behavior in multi-core SoC.