Hardware Implementation Of 128-bit Floating Point Exponential Function

With the rapid development of the world's informatization process,the amount of data required for computer processing and calculation has become very large.Floating-point numbers have a wide range of representation characteristics,so floating-point calculations are increasingly used in the field of high-precision computing,and the calculation of floating-point numbers has become increasingly important.Floating-point transcendental functions are widely used in astronomy,surveying,and other fields.In the design of integrated circuits,due to the constraints of manufacturing processes and chip area,the traditional floating-point hardware arithmetic unit's architecture is simple and slow,and it is difficult to implement complex calculations of transcendental functions.Therefore,software methods are often used to achieve complexity floating-point arithmetic.The improvement of integrated circuit technology provides a basis for designing complex floating-point transcendental function arithmetic units.Therefore,designing faster and more accurate floating-point hardware arithmetic units has become a subject that must be faced in integrated circuit design.The exponential function is the most widely used function among transcendental functions.Based on Coordinate Rotation Digital Compute(CORDIC),this paper proposes a 128-bit floating-point exponential function hardware parallel processing architecture.An improved four-time prediction CORDIC algorithm is used in the architecture to predict the symbol value of four iterations on one clock,which can reduce the iterative operation cycle,improve the algorithm speed,and solve the problem that the CORDIC algorithm has more iterations under high-precision calculations.In the 128-bit floating-point exponential operation,the originally required at least 128 iterations were reduced to 37 times,which greatly reduced the algorithm operation cycle and improved the operation efficiency of the algorithm.Compared to the traditional CORDIC algorithm,which can only determine the symbol based on the value of the next iteration,the four-prediction CORDIC algorithm determines the symbol from the overall value of the four iterations,so it can better guarantee the calculation accuracy and is more suitable for high-precision floating-point exponential functions calculation.This paper implements the hardware circuit structure design of a 128-bit floating-point exponential function operation unit.The overall structure is divided into three parts: a preprocessing module,an exponential function mantissa iteration module,and a regularization module.The preprocessing module is responsible for exception analysis,and processes the input 128-bit floating-point number,converts the input floating-point number to fixed-point number,calculates the exponent value of the result through the calculation unit,and outputs the initial calculated value of the mantissa iteration.The exponential function mantissa calculation module uses the improved four-time prediction CORDIC algorithm for iterative calculation,which is the core of this algorithm.The fixed-point number obtained by preprocessing is input to the mantissa iteration module,and after a certain clock period,the iteration results are hyperbolic sine and cosine value corresponding to the pre-processing fixed-point number.The regularization module is responsible for adding the calculation results of the mantissa iteration module to obtain the mantissa value of the calculation result.The mantissa value,exponent value and sign bit are integrated into a standard floating-point number format through a leading zero detection circuit and a subtractor.The paper uses Verilog language to program and complete the hardware circuit design.Under the TSMC 65 nm process,Synopsys' comprehensive design tool is used for simulation synthesis.This experiment uses Python to generate 100,000 sets of random floating-point numbers for comparison verification.After testing,the calculation result of this algorithm satisfies the 113-bit full-precision output when the input and output are 128-bit floating-point numbers.At 500 MHz operating frequency,the hardware area consumption is 0.66 mm~2,the hardware power consumption is 62.65 m W,and the calculation period is 37 clocks.In summary,the paper can achieve the expected goal and complete the design of the 128-bit highprecision floating-point exponential function unit.