Hardware Design Of 128-bit Floating-point Logarithmic Processing Unit

A large number of floating-point transcendental function calculations are needed in scientific calculation,meteorological prediction and other application scenarios.The current hardware processor does not contain the basic operation hardware units of transcendental function,and still uses the software library function to transform the transcendental function into approximate algebraic function by iterative approximation.This method often needs to call subroutines of various floating-point operations frequently which results in poor operation efficiency.In addition,the requirements for calculation accuracy are also increasing with the complexity of scientific research.The general double-precision calculation cannot fulfill the application requirements of military and astronomical fields,128-bit or higher precision floating-point computing requirements are also being proposed.With the continuous improvement of the level of integrated circuit production technology,the number of circuit gates that the processor can integrate is increasing,the power consumption and area per gate are exponentially decreasing,and the full hardware implementation of the transcendental function calculation becomes a new direction of improving performance.Logarithmic operation is one of the most widely used functions in transcendental functions.This paper completes the hardware IP design for the 128-bit high-precision floating-point-to-number operation unit.This paper analyzes and improves the algorithm of CORDIC(COordinate Rotation DIgital Computer)and designs a new Quadruple-step Parallel Branch CORDIC algorithm for 128-bit floating-point logarithmic operation.The 128-bit floating point contains 113 bits of precision,and the improved algorithm proposed in the paper supports 4-bit parallel calculations per step.Based on the CORDIC algorithm in the hyperbolic coordinate system,the y value in the algorithm is always negative,and the value of the iteration direction?is changed from{-1,1}to{0,1}.The prediction of the four-step iteration direction is performed each time by calculating x,y,and z in parallel.Due to the value characteristics of?and y,the next four iteration directions can be obtained directly from the parallel calculation results.According to the prediction result of the iterative direction,the correct set of parallel calculation results is directly selected as the output of this iteration.The algorithm solves the defect that the original algorithm requires a large number of calculation cycles and improves the operation efficiency.Modular design is used in the design process.According to the characteristics of floating-point logarithmic operation,the design of the whole floating-point logarithmic operation unit is divided into four modules,which are pre-processing module,mantissa logarithmic operation module,exponent multiplication module and addition merge module.The preprocessing module is mainly responsible for decoding the input floating-point number and converting the floating point calculation into fixed point calculation.At the same time,the input abnormal value is detected and processed.As the core module of this design,the fixed-point logarithm operation module implements the hardware implementation of the Quadruple-step Iterative Branch CORDIC algorithm,and improves the operation speed by means of parallel prediction calculation.The exponent multiplication module uses a radix-8 Booth multiplication and carry look-ahead adder to design a high-speed dedicated multiplier to process the exponent portion of the input.Finally,the results of the above two modules are delivered into the addition merge module.The results are combined by a carry look-ahead adder,rounded and normalized to obtain the final result.This design uses the Verilog language for code writing and Synopsys'design tools to simulate and synthesis in the TSMC 65nm process.20 million sets of 128-bit floating-point random data were generated using the code.All the calculation results can reach the effective precision of 113 bits,which means full-precision calculation is realized.The processing unit only needs 37 clock cycles to finish the calculation once.The synthesis result shows that at the working frequency of 500MHz,the total hardware area is about 0.72mm~2,and the total power is about 62.38mW.In conclusion,this design achieves the goal and completes the design of 128bit high precision floating point logarithmic arithmetic unit.