Design And Implementation Of AXI4 Bus Interface Based On Python Hardware Description

With the rapid development of information-technology industry in recent years,the integration and complexity of circuits have increased exponentially.SoC technology has emerged at that moment.The emergence of on-chip bus technology has made important contributions to SoC design.However,the design process of on-chip bus involves multiple development languages and environment,with large professional span and high development threshold,requiring multiple people to cooperate,leading to longer design cycles,which has become an important bottleneck that hinders the rapid development of integrated circuits.Object-oriented agile design has become the main trend of international large scale integrated circuits.This paper is dedicated to the research of the AXI4 bus protocol,which has the highest market share.The master and slave interfaces of AXI-Full,AXI-Lite,and AXI-Stream are designed and implemented respectively based on Python language.Besides,the comprehensive functional verification has been established based on the verification methed.Finally,a neural network algorithm IP core named LeNet-5 has been added an AXI4 bus interface to designed as a coprocessor,and then we designed a Python driver to deploy it running in the FPGA correctly.The entire design process breaks the boundary between the high-level language and the underlying hardware.The specific research contents of this paper are as follows:1.The AXI4 bus protocol standard is researched,and the characteristics,channel structure and signals,handshake mechanism and basic read and write transmission timing process of the three types of bus included AXI-Full,AXI-Lite and AXI-Stream is analyzed and compared in detail respectively.Then an agile design process of AXI4 bus interface based on Python hardware description is proposed.2.The open source hardware design framework Py HCL is researched.The master and slave interface of three types of bus included AXI-Full,AXI-Lite,AXI-Stream is designed and implemented respectively based on Python language.Then the simulation test of read and write communication between interfaces is established in Vivado software.3.The open source hardware verification framework Py UVM is researched.A comprehensive functional verification of the master and slave interface of three types of bus included AXI-Full,AXI-Lite,AXI-Stream is completed respectively based on Python language and UVM verification methodology,reaching 100% coverage rate.4.The open source framework PYNQ is researched.A neural network algorithm IP core named LeNet-5 has been added an AXI bus interface to design as a coprocessor.At the same time we design a Python driver to provide a more friendly operation interface for it,and finally deploy the coprocessor to run correctly in the PYNQ-Z2 development board.The design and implementation of the AXI4 bus interface based on Python hardware description replacing the complicated process of the on-chip bus design with a high-level language,realizing full-stack development with Python,which greatly reduces the threshold of hardware development and provides a new idea for the agile design of integrated circuits.