Research And Design Of LC Voltage-controlled Oscillator With Tail Current Shaping

As the critical module of PLL in satellite navigation system receiver,VCO is used to generate local oscillator signals and achieve signal channel selection and spectrum shifting,and its phase noise performance directly determines the performance of the whole system.Therefore,low phase noise has always been the key and difficult point in the design of inductive capacitor(LC)voltage-controlled oscillators.Although some ideas have been proposed to improve the phase noise performance by reducing the current conduction angle,the effect of the reduced conduction angle has not been explained in detail.Therefore,in order to solve the above problems,this paper studies the relationship between current conduction angle and phase noise and proposes a low phase noise voltage-controlled oscillator structure.In this paper,the impact of the current conduction angle on the phase noise of the 1?1)~2region and 1?1)~3 region is quantitatively analyzed from the perspective of impulse sensitivity function and noise modulation function.The results show that in the 1?1)~2 region,the phase noise decreases as the conduction angle decreases,and then deteriorates as the power spectrum density of the noise current increases.Similarly,the 1?1)~3 region phase noise first decreases with the conduction angle decreases,but as the phase shift of the impulse sensitive function and the noise modulation function is serious,the up-conversion of flicker noise caused by the AM-PM conversion and the Groszkowski effect is intensified.Therefore,in the design of low phase noise voltage-controlled oscillators,the phase noise can be optimized by appropriately reducing the current conduction angle.This paper designs a tail current shaping voltage-controlled oscillator with self-starting function,which has the characteristics of fast start-up and low phase noise.The output signal is coupled to the gate of the tail transistor by means of capacitance to realize the shaping of the tail current so as to inject more current when ISF is minimum,so that the conversion of noise is reduced.The lower bias voltage reduces the current conduction angle and the duty cycle of the noise modulation function,so as to reduce the phase noise.This oscillator has an additional starting tail current source,in order to enable the oscillator to start quickly at the beginning and turn off as the bias voltage decreases after stable oscillation,so as to fast start-up.This design is based on the Cadence Virtuoso platform,the TSMC 180nm process is used to implement the overall circuit design,the voltage source is 1.8 V.The layout area of the final design is 1039.7?m×649.1?m,The results show that the phase noise at the oscillation frequency of 2 GHz is-81.63 d Bc/Hz at 10 k Hz and-131.58 d Bc/Hz at 1 MHz.