A Research Of Multi-channel Digital Signal 20GS/s Timing Analysis Technology

With the improvement of the working frequency of digital system, we need more rapid and accurate observation. In order to test the digital circuit, as a data domain testing instrument, the timing analysis rate of the logic analyzer urgently needs to be improved. As the analysis rate becomes more sophisticated, the synchronous problem of multi-channel becomes particularly prominent; especially in high speed digital circuit the synchronization performance will directly affect the results of testing and analysis.Based on the development of high performance logic analyzer timing analysis module, this thesis focuses on the research for 20GS/s timing analysis and multichannel synchronization. This thesis also presents the hardware overall scheme of 16-channel 20GS/s timing analysis module, and completes 20GS/s timing analysis circuit design, 16-channel synchronous design. The main contents are as follows:(1) Analyzing shift sampling, tree-shape sampling, multi-phase sampling of these three high-speed digital signal sampling technology to determine the scheme of 20GS/s timing sampling based on FPGA’s high-speed receiver port, thus achieving the design of 20GS/s timing sampling circuit.(2) Using sampling clock generation technology, high precision clock delay technology, digital logic-level matching technology, realize the design of clock circuit, digital signal level-matching and fan out circuit of 20GS/s timing analysis. Combined with FPGA-based sequential logic circuit and combinational logic circuit, and completed design of high-speed signal trigger identification circuit, the trigger position judging circuit. At the same time, combined with the acquisition main status jumping based on the trigger signal, completed the data storage control circuit for high bits parallel sampled data.(3) According to the impact factors of multi-channel synchronization such as channel circuit, clock circuit, sampling circuit, trigger and storage circuit, determine the channel circuit consistent scheme, clock synchronization scheme, sampling synchronization scheme, trigger synchronization scheme. Then, the design of multi-channel synchronous is completed.(4) Completing the design of channel synchronous with synchronous signal calibration circuit. Based on the calibration data to realize the design of trigger synchronous, particularly improves the recognition efficiency for pattern trigger; realizing the design of the clock synchronization according to the low jitter and low skew requirement; improving the hardware acquisition process control for the channels acquisition synchronization between two FPGA’s.